AT&T 3B2/300 Technical Reference Manual page 350

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Memory Management Unit
The Memory Management Unit (MMU) on the CM518A System Board is a WE 32101 Memory
Management Unit.
Note: The WE 32100 chipset is covered in the "CM190A/ED-4C637-30 System Board"
section for Version 2 system boards. Refer to that section for detailed information on
the CPU/MMU/MAU chips of the CM518A System Board.
The MMU on a CM518B/C System Board is a WE 32201 Memory Management Unit. Figure 3-29
shows how the MMU connects to the system. The internal MMU address spectrum is shown in Figure
3-30. Figure 2-31 shows the virtual to physical address translation for paged segments.
The MMU manipulates the microprocessor's address space by translating the virtual microprocessor
addresses into physical address information. The 32-bit address can access over 4 gigabytes (2
32 )
of
system memory or peripherals. The MMU also supports demand paged and demand segmented virtual
memory. This permits large programs to efficiently use physical memory space. The WE 32201 MMU
comes with an on-chip 4K byte, 2-way, set-associative instruction/data cache that returns data with
zero wait states on CPU virtual to physical memory accesses.
The MMU divides the virtual address space into four sections. Each of these four sections can be
subdivided into as many as 8K segments per section. These segments are paged and are mapped into
the physical address space by the MMU. A paged segment can contain up to sixty-four 2K byte pages.
Since segments are a multiple of pages, they always start on page boundaries.
Virtual addresses are relative addresses of an active process. Physical addresses are addresses that
the main store controller can interpret as the true physical location of the memory. The function of the
MMU is to translate virtual addresses to physical addresses. The address of each byte within a 2K byte
block (offset) is not translated because the smallest size data block that can be placed in the main store
by the MMU is 2K bytes. Therefore, the lower 11 bits of the virtual address spectrum and the
lower 11 bits of the physical address spectrum are the same. The MMU stores information describing
the physical location of blocks of 2K bytes of process data. The description locations are stored in the
MMU caches. The MMU uses four caches: ID Number Cache (IDNC), Current ID Number Registers
(CIDNR), Segment Descriptor Cache (SOC) and Page Descriptor Cache (PDC).
Virtual address space is further described in Appendix A.
FUNCTIONAL DESCRIPTION 3-97