AT&T 3B2/300 Technical Reference Manual page 265

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Input/Output Bus System
Input/Output Bus System Features
The Input/Output (1/0) bus system is an asynchronous, nonmultiplexed bus providing a flexible
interface for feature cards. The system can directly address up to 16 megabytes on this bus via 24-bit
address and either 8-bit or 16-bit data transfers. Other features include three interrupt priority levels
and a single level of "distributed" bus arbitration.
The 1/0 bus system also supports a special Multiple Access Transfer Cycle in which more than one
data transfer (bus access) can be made by the same feature card in a single bus cycle. After a feature
card receives a bus acknowledge signal, the feature card can hold the 1/0 bus for no more than
4 microseconds. Multiple accesses are executed without bus arbitration and are thus a high
performance consideration. A maximum of 4 data half-words can be transferred per one arbitration.
The Version 3 computers have an enhanced 1/0 bus. This bus supports sequential access-a subset
of multiple word transfers. Up to 32 data transfers may be done simultaneously using the sequential
access mode.
Peripheral Controllers
Peripheral controllers are feature cards connected to the system board via the 1/0 bus. There are
two types of peripheral controller feature cards that connect to the 1/0 bus: programmed and
intelligent. Feature cards requiring only power and ground connections are passive cards. Intelligent
controllers can use a Bus Abort Feature (BAF) to prevent the INTEL 80186 Microprocessor from being
locked up while waiting for an 1/0 bus request to be acknowledged. Not all intelligent controllers
require the use of the BAF.
Programmed Controllers.
Programmed controllers are feature cards containing programmable
registers that can be written or read by the system board CPU. These feature cards have limited "on
card" intelligence and operate in response to programming by the system board CPU. Programmed
controllers are generally slave devices with respect to the system board CPU. After programming by
the system board CPU, these types of feature cards can for example be a bus master.
Feature cards functioning as programmed controllers can provide the following:
• An 8- or 16-bit Feature Card Identification (ID) Code register. This register uniquely identifies the
card and is intended to be read by the system board. The size of the register is determined by
the word size of the feature card. The 8-bit feature cards use an 8-bit ID code register; 16-bit
feature cards use a 16-bit ID code register.
• An optional feature card control register of up to 16 bits.
• An optional feature card status register of up to 16 bits.
• An optional 8-bit interrupt vector register. Any feature card with the capability to interrupt the
system board CPU responds with a vector when the interrupt request is acknowledged.
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