AT&T 3B2/300 Technical Reference Manual page 356

- - - - - - - - - - - - - - - - - - - - - - - - - - - FUNCTIONAL DESCRIPTION
Peripheral Mode.
In the peripheral mode of MMU operation, the MMU is accessed as a
memory-mapped peripheral. In this mode, internal MMU registers and logic elements are read and
write accessible by the system board CPU. All peripheral mode accesses are word (32-bit) accesses.
When the system board CPU asserts the MMU Chip Select (MMUCS[O]), the MMU is in the peripheral
mode. The internal MMU address spectrum is shown in Figure 3-30. In the peripheral mode, physical
address bits 31-00 are interpreted as follows by the MMU.
PERIPHERAL MODE ADDRESS FIELDS
BITS
31 - 12 11 -08 07- 02 01 -00
FIELD RESERVED
ENTITY INDEX RESERVED
The peripheral mode address fields are defined in the following paragraphs.
RESERVED Bits 31-12, 01, and 00 are ignored by the MMU. These bits are negated (treated
as zeros).
ENTITY
INDEX
Bits 11-08 are used to select the internal MMU circuit (entity) to be accessed. The
decode of bits 11-08 is as follows.
BITS 11 - 08 SELECTED MMU DEVICE
0000 SEGMENT DESCRIPTOR CACHE BITS 31-00
0001 SEGMENT DESCRIPTOR CACHE BITS 63-32
0010 PAGE DESCRIPTOR CACHE BITS 31-00
OOll
PAGE DESCRIPTOR CACHE BITS 63-32
0100 FLUSH DAT A CACHE REGISTER
0101 RESERVED
OllO
SECTION RAM A
0111
SECTION RAM B
1000
FAULT CODE REGISTER
1001 FAULT ADDRESS REGISTER
1010 CONFIGURATION REGISTER
lOll VIRTUAL ADDRESS REGISTER
llOO ID NUMBER CACHE
llOI CURRENT ID NUMBER REGISTER
1110 FLUSH ID NUMBER REGISTER
1 ll 1 VERSION REGISTER
Bits 07-02 are used to index each addressable entity. Bits 07-02 are ignored
when register are accessed. Bits 07-02 are used when segment or page descriptor
caches are accessed. Bits 03 and 02 are used for section RAM accesses.
FUNCTIONAL DESCRIPTION 3-103