Dynamic Reconfiguration Port; Functional Description; Ports And Attributes; Using The Drp Interface - Xilinx Virtex-6 FPGA User Manual

Chapter 2: Shared Transceiver Features

Dynamic Reconfiguration Port

Functional Description

The dynamic reconfiguration port (DRP) allows the dynamic change of parameters of the
GTHE1_QUAD primitive. The DRP interface is a processor-friendly synchronous interface
with an address bus (DADDR) and separated data buses for reading (DO) and writing (DI)
configuration data to the GTH Quad. An enable signal (DEN), a read/write signal (DWE),
and a ready/valid signal (DRDY) are the control signals that implement read and write
operations, indicate operation completion, or indicate the availability of data. Refer to
UG360, Virtex-6 FPGA Configuration User Guide for detailed descriptions and timing
diagrams of the DRP operations.

Ports and Attributes

Table 2-15
Table 2-15: DRP Ports
Port Dir Clock Domain
DADDR[15:0] In
DCLK In
DEN In
DI[15:0] In
DISABLEDRP In
DRPDO[15:0] Out
DRDY Out
DWE In

Using the DRP Interface

To enable the DRP interface, the DISABLEDRP port is driven Low. When the DRP interface
is enabled, the management interface must be disabled.
Note:
and the management interface, the user must wait two DCLK cycles for the change to take effect
before accessing the registers.
70
defines the DRP ports.
DCLK This input bus is the DRP address bus.
N/A This input is the DRP interface clock. It is also used as the management
interface clock when the management interface is enabled. This clock must
be connected and available all the time for the GTHE1_QUAD primitive to
initialize properly, even if the DRP or the management interface is not used
in the design.
DCLK This input is the DRP enable signal.
0: No read or write operation performed.
1: Enables a read or write operation.
DCLK This input bus is the data bus for writing configuration data from the FPGA
logic resources to the GTHE1_QUAD primitive.
DCLK This input switches between the DRP and the management interface blocks.
0: DRP interface is selected.
1: Management interface is selected.
DCLK This output bus is the data bus for reading configuration data from the
GTHE1_QUAD primitive to the FPGA logic resources.
DCLK When asserted, this output indicates operation is complete for write
operations and data is valid for read operations.
DCLK This input is the DRP write enable:
0: Read operation when DEN is 1.
1: Write operation when DEN is 1.
When the setting on the DISABLEDRP port is changed to switch between the DRP interface
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Description
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010