Chapter 3: Microblaze Signal Interface Description; Overview - Xilinx MicroBlaze Reference Manual

MicroBlaze Signal Interface Description
This chapter describes the types of signal interfaces that can be used to connect MicroBlaze™.

Overview

The MicroBlaze core is organized as a Harvard architecture with separate bus interface units for data
and instruction accesses. The following four memory interfaces are supported: Local Memory Bus
(LMB), the AMBA
Bus (PLB), and Xilinx CacheLink (XCL). The LMB provides single-cycle access to on-chip dual-
port block RAM. The AXI4 and PLB interfaces provide a connection to both on-chip and off-chip
peripherals and memory. The ACE interfaces provide cache coherent connections to memory. The
CacheLink interface is intended for use with specialized external memory controllers. MicroBlaze
also supports up to 16 Fast Simplex Link (FSL) or AXI4-Stream interface ports, each with one
master and one slave interface.
Features
MicroBlaze can be configured with the following bus interfaces:
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MicroBlaze Processor Reference Guide
UG081 (v14.7)
®
AXI4 interface (AXI4) and ACE interface (ACE), the IBM Processor Local
The AMBA AXI4 Interface for peripheral interfaces, and the AMBA AXI4 or ACE Interface
for cache interfaces (see ARM
0022E).
A 32-bit version of the PLB V4.6 interface (see IBM's 128-Bit Processor Local Bus
Architectural Specifications, Version 4.6).
LMB provides simple synchronous protocol for efficient block RAM transfers
FSL or AXI4-Stream provides a fast non-arbitrated streaming communication mechanism
XCL provides a fast slave-side arbitrated streaming interface between caches and external
memory controllers
Debug interface for use with the Microprocessor Debug Module (MDM) core
Trace interface for performance analysis
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® ®
AMBA AXI and ACE Protocol Specification, ARM IHI
Chapter 3
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