Xilinx MicroBlaze Reference Manual page 216

Chapter 5: MicroBlaze Instruction Set Architecture
msrclr
Read MSR and clear bits in MSR
msrclr
1 0 0 1 0 1
0 6
Description
Copies the contents of the special purpose register MSR into register rD.
Bit positions in the IMM value that are 1 are cleared in the MSR. Bit positions that are 0 in the IMM
value are left untouched.
When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged
for all IMM values except those only affecting C. This means that if the instruction is attempted in
User Mode (MSR[UM] = 1) in this case a Privileged Instruction exception occurs.
Pseudocode
Registers Altered
•
•
•
Latency
•
Notes
MSRCLR will affect the Carry bit immediately while the remaining bits will take effect one cycle
after the instruction has been executed. When clearing the IE bit, it is guaranteed that the processor
will not react to any interrupt for the subsequent instructions.
The value read from MSR may not include effects of the immediately preceding instruction
(dependent on pipeline stall behavior). An instruction that does not affect MSR must precede the
MSRCLR instruction to guarantee correct MSR value. This applies to both the value copied to
register rD and the changed MSR value itself.
The immediate values has to be less than 2
14
2
and.bits 18 to 31 otherwise.
This instruction is only available when the parameter C_USE_MSR_INSTR is set to 1.
When clearing MSR[VM] the instruction must always be followed by a synchronizing branch
instruction, for example BRI 4.
216
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rD, Imm
rD 1 0 0 0 1 0
11
if MSR[UM] = 1 and IMM
←
ESR[EC] 00111
else
←
(rD) (MSR)
← ∧ (
(MSR) (MSR) IMM))
rD
MSR
ESR[EC], in case a privileged instruction exception is generated
1 cycle
otherwise. Only bits 17 to 31 of the MSR can be cleared when C_USE_MMU >= 1 (User Mode),
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Imm15
16 17
≠
0x4 then
15
when C_USE_MMU >= 1 (User Mode), and less than
MicroBlaze Processor Reference Guide
31
UG081 (v14.7)