Xilinx MicroBlaze Reference Manual page 97

Table 3-1: Summary of MicroBlaze Core I/O
M_AXI_DP_AWID
M_AXI_DP_AWADDR
M_AXI_DP_AWLEN
M_AXI_DP_AWSIZE
M_AXI_DP_AWBURST
M_AXI_DP_AWLOCK
M_AXI_DP_AWCACHE
M_AXI_DP_AWPROT
M_AXI_DP_AWQOS
M_AXI_DP_AWVALID
M_AXI_DP_AWREADY
M_AXI_DP_WDATA
M_AXI_DP_WSTRB
M_AXI_DP_WLAST
M_AXI_DP_WVALID
M_AXI_DP_WREADY
M_AXI_DP_BID
M_AXI_DP_BRESP
M_AXI_DP_BVALID
M_AXI_DP_BREADY
M_AXI_DP_ARID
M_AXI_DP_ARADDR
M_AXI_DP_ARLEN
M_AXI_DP_ARSIZE
M_AXI_DP_ARBURST
M_AXI_DP_ARLOCK
M_AXI_DP_ARCACHE
M_AXI_DP_ARPROT
M_AXI_DP_ARQOS
M_AXI_DP_ARVALID
M_AXI_DP_ARREADY
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Signal Interface
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
M_AXI_DP
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MicroBlaze I/O Overview
I/O Description
O Master Write address ID
O Master Write address
O Master Burst length
O Master Burst size
O Master Burst type
O Master Lock type
O Master Cache type
O Master Protection type
O Master Quality of Service
O Master Write address valid
I Slave Write address ready
O Master Write data
O Master Write strobes
O Master Write last
O Master Write valid
I Slave Write ready
I Slave Response ID
I Slave Write response
I Slave Write response valid
O Master Response ready
O Master Read address ID
O Master Read address
O Master Burst length
O Master Burst size
O Master Burst type
O Master Lock type
O Master Cache type
O Master Protection type
O Master Quality of Service
O Master Read address valid
I Slave Read address ready
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