Xilinx MicroBlaze Reference Manual page 44

Chapter 2: MicroBlaze Architecture
Processor Version Register (PVR)
The Processor Version Register is controlled by the C_PVR configuration option on MicroBlaze.
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When read with the MFS instruction the PVR is specified by setting Sa = 0x200x, with x being the
register number between 0x0 and 0xB.
Table 2-24
Table 2-24: Processor Version Register 0 (PVR0)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14:15
16:23
24:31
44
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When C_PVR is set to 0 (None) the processor does not implement any PVR and
MSR[PVR]=0.
When C_PVR is set to 1 (Basic), MicroBlaze implements only the first register: PVR0, and if
set to 2 (Full), all 13 PVR registers (PVR0 to PVR12) are implemented.
through Table 2-35
Bits Name
CFG PVR implementation:
0 = Basic, 1 = Full
BS Use barrel shifter
DIV Use divider
MUL Use hardware multiplier
FPU Use FPU
EXC Use any type of exceptions
ICU Use instruction cache
DCU Use data cache
MMU Use MMU
BTC Use branch target cache
ENDI Selected endianness:
0 = Big endian, 1 = Little endian
FT Implement fault tolerant features
SPROT Use stack protection
REORD Implement reorder instructions
Reserved
MBV MicroBlaze release version code
0x1 = v5.00.a
0x2 = v5.00.b
0x3 = v5.00.c
0x4 = v6.00.a
0x6 = v6.00.b
0x5 = v7.00.a
0x7 = v7.00.b
0x8 = v7.10.a
0x9 = v7.10.b
0xA = v7.10.c
0xB = v7.10.d
0xC = v7.20.a
0xD = v7.20.b
0xE = v7.20.c
USR1 User configured value 1
www.xilinx.com
provide bit descriptions and values.
Description
Based on C_PVR
C_USE_BARREL
C_USE_DIV
C_USE_HW_MUL > 0 (None)
C_USE_FPU > 0 (None)
Based on C_*_EXCEPTION
Also set if C_USE_MMU > 0 (None)
C_USE_ICACHE
C_USE_DCACHE
C_USE_MMU > 0 (None)
C_USE_BRANCH_TARGET_CACHE
C_ENDIANNESS
C_FAULT_TOLERANT
C_USE_STACK_PROTECTION
C_USE_REORDER_INSTR
0
Release Specific
0xF = v7.20.d
0x10 = v7.30.a
0x11 = v7.30.b
0x12 = v8.00.a
0x13 = v8.00.b
0x14 = v8.10.a
0x15 = v8.20.a
0x16 = v8.20.b
0x17 = v8.30.a
0x18 = v8.40.a
0x19 = v8.40.b
0x1A = v8.50.a
0x1C = v8.50.b
0x1E = v8.50.c
C_PVR_USER1
MicroBlaze Processor Reference Guide
Value
UG081 (v14.7)