Xilinx MicroBlaze Reference Manual page 162

Chapter 5: MicroBlaze Instruction Set Architecture
add
Arithmetic Add
add
addc
addk
addkc
0 0 0 K C 0
0 6
Description
The sum of the contents of registers rA and rB, is placed into register rD.
Bit 3 of the instruction (labeled as K in the figure) is set to one for the mnemonic addk. Bit 4 of the
instruction (labeled as C in the figure) is set to one for the mnemonic addc. Both bits are set to one
for the mnemonic addkc.
When an add instruction has bit 3 set (addk, addkc), the carry flag will Keep its previous value
regardless of the outcome of the execution of the instruction. If bit 3 is cleared (add, addc), then the
carry flag will be affected by the execution of the instruction.
When bit 4 of the instruction is set to one (addc, addkc), the content of the carry flag (MSR[C])
affects the execution of the instruction. When bit 4 is cleared (add, addk), the content of the carry
flag does not affect the execution of the instruction (providing a normal addition).
Pseudocode
Registers Altered
•
•
Latency
1 cycle
Note
The C bit in the instruction opcode is not the same as the carry bit in the MSR.
The "add r0, r0, r0" (= 0x00000000) instruction is never used by the compiler and usually indicates
uninitialized memory. If you are using illegal instruction exceptions you can trap these instructions
by setting the MicroBlaze parameter C_OPCODE_0x0_ILLEGAL=1.
162
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rD, rA, rB
rD, rA, rB
rD, rA, rB
rD, rA, rB
rD rA
1
1
if C = 0 then
←
(rD) (rA) + (rB)
else
←
(rD) (rA) + (rB) + MSR[C]
if K = 0 then
←
MSR[C] CarryOut
rD
MSR[C]
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Add
Add with Carry
Add and Keep Carry
Add with Carry and Keep Carry
rB 0 0 0 0 0 0 0 0 0 0 0
1 2
6 1
MicroBlaze Processor Reference Guide
3
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UG081 (v14.7)