Xilinx MicroBlaze Reference Manual page 125

DCACHE_FSL_OUT_Control
DCACHE_FSL_OUT_Full
CacheLink Transactions
All individual CacheLink accesses follow the FSL FIFO based transaction protocol:
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•
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For details on the generic FSL protocol, please see the Fast Simplex Link (FSL) Bus (DS449) data-
sheet in the Xilinx EDK IP Documentation.
The CacheLink solution uses one incoming (slave) and one outgoing (master) FSL per cache
controller. The outgoing FSL is used to send access requests, while the incoming FSL is used for
receiving the requested cache lines. CacheLink also uses a specific encoding of the transaction
information over the FSL data and control signals.
The cache lines used for reads in the CacheLink protocol are 4 or 8 words long. Each cache line is
either fetched with the critical word first, or in linear order, depending on the selected interface
protocol.
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MicroBlaze Processor Reference Guide
UG081 (v14.7)
Table 3-12: MicroBlaze Cache Link Signals (Continued)
Signal Name
Access information is encoded over the FSL data and control signals (e.g.
DCACHE_FSL_OUT_Data, DCACHE_FSL_OUT_Control, ICACHE_FSL_IN_Data,
and ICACHE_FSL_IN_Control)
Information is sent (stored) by raising the write enable signal (e.g.
DCACHE_FSL_OUT_Write)
The sender is only allowed to write if the full signal from the receiver is inactive (e.g.
DCACHE_FSL_OUT_Full = 0). The full signal is not used by the instruction cache
controller.
The use of ICACHE_FSL_IN_Read and DCACHE_FSL_IN_Read depends on the
selected interface protocol:
With the IXCL and DXCL protocol, information is received (loaded) by raising the read
♦
signal. The signal is low, except when the sender signals that new data exists.
♦ With the IXCL2 and DXCL2 protocol, lowering the read signal indicates that the receiver
is not able to accept new data. New data is only read when the read signal is high, and the
sender signals that data exists. Once a burst read has started, the read signal is not lowered.
The receiver is only allowed to read as long as the sender signals that new data exists (e.g.
ICACHE_FSL_IN_Exists = 1)
Critical word first is used by the IXCL and DXCL protocol, selected when
C_ICACHE_INTERFACE = 0 (IXCL) and C_DCACHE_INTERFACE = 0 (DXCL),
respectively. Each cache line is expected to start with the critical word first (that is, if an access
to address 0x348 is a miss with a 4 word cache line, then the returned cache line should have
the following address sequence: 0x348, 0x34c, 0x340, 0x344). The cache controller forwards
the first word to the execution unit as well as stores it in the cache memory. This allows
execution to resume as soon as the first word is back. The cache controller then follows
through by filling up the cache line with the remaining 3 or 7 words as they are received.
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Xilinx CacheLink (XCL) Interface Description
Description
FSL control-bit to D-side read
access FSL. Used with
address bits [30 to 31] for
read/write, byte enable and
burst write encoding.
FSL access buffer for D-side
read accesses is full
VHDL Type Direction
std_logic output
std_logic input
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