Xilinx MicroBlaze Reference Manual page 145

Table 3-18: MPD Parameters (Continued)
Parameter Name
C_USE_EXT_NM_BRK
C_USE_BRANCH_TARGET_CACHE
C_BRANCH_TARGET_CACHE_SIZE
C_M_AXI_DP_
THREAD_ID_WIDTH
C_M_AXI_DP_DATA_WIDTH
C_M_AXI_DP_ADDR_WIDTH
C_M_AXI_DP_
SUPPORTS_THREADS
C_M_AXI_DP_SUPPORTS_READ
C_M_AXI_DP_SUPPORTS_WRITE
C_M_AXI_DP_SUPPORTS_
NARROW_BURST
C_M_AXI_DP_PROTOCOL
C_M_AXI_DP_
EXCLUSIVE_ACCESS
C_INTERCONNECT_
M_AXI_DP_READ_ISSUING
C_INTERCONNECT_
M_AXI_DP_WRITE_ISSUING
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Feature/Description
Enable external non-
maskable break handling
Enable Branch Target
5
Cache
Branch Target Cache size:
5
0 = Default
1 = 8 entries
2 = 16 entries
3 = 32 entries
4 = 64 entries
5 = 512 entries
6 = 1024 entries
7 = 2048 entries
Data side AXI thread ID
width
Data side AXI data width
Data side AXI address
width
Data side AXI uses threads
Data side AXI support for
read accesses
Data side AXI support for
write accesses
Data side AXI narrow
burst support
Data side AXI protocol
Data side AXI exclusive
access support
Data side AXI read
accesses issued
Data side AXI write
accesses issued
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MicroBlaze Core Configurability
EDK
Allowable Default Tool
Values Value Assig
ned
yes
0,1 0
0,1 0
0-7 0
1 1
32 32
32 32
0 0
1 1
1 1
0 0
AXI4, AXI4 yes
AXI4LITE LITE
0,1 0
1 1
1 1
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VHDL Type
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
string
integer
integer
integer
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