Xilinx MicroBlaze Reference Manual page 37

Zone Protection Register (ZPR)
The Zone Protection Register is used to override MMU memory protection defined in TLB entries.
It is controlled by the C_USE_MMU configuration option on MicroBlaze. The register is only
implemented if C_USE_MMU is greater than 1 (User Mode), C_AREA_OPTIMIZED is set to 0, and
if the number of specified memory protection zones is greater than zero (C_MMU_ZONES > 0). The
implemented register bits depend on the number of specified memory protection zones
(C_MMU_ZONES). When accessed with the MFS and MTS instructions, the ZPR is specified by
setting Sa = 0x1001. The register is accessible according to the memory management special
registers parameter C_MMU_TLB_ACCESS.
provides bit descriptions and reset values.
0 2 4 6
↑ ↑ ↑ ↑
ZP0 ZP1 ZP2 ZP3
Table 2-19: Zone Protection Register (ZPR)
0:1
2:3
...
30:31
MicroBlaze Processor Reference Guide
UG081 (v14.7)
8 10 12 14
↑ ↑ ↑
ZP4 ZP5 ZP6
Figure 2-13: ZPR
Bits Name
ZP0 Zone Protect
ZP1 User mode (MSR[UM] = 1):
... 00 = Override V in TLB entry. No access to the page is
allowed
ZP15
01 = No override. Use V, WR and EX from TLB entry
10 = No override. Use V, WR and EX from TLB entry
11 = Override WR and EX in TLB entry. Access the page
as writable and executable
Privileged mode (MSR[UM] = 0):
00 = No override. Use V, WR and EX from TLB entry
01 = No override. Use V, WR and EX from TLB entry
10 = Override WR and EX in TLB entry. Access the page
as writable and executable
11 = Override WR and EX in TLB entry. Access the page
as writable and executable
Read/Write
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Figure 2-13 illustrates the ZPR register and
16 18 20
↑ ↑ ↑ ↑
ZP7 ZP8 ZP9 ZP10
Description
Registers
Table 2-19
22 24 26 28
↑ ↑ ↑ ↑
ZP11 ZP12 ZP13 ZP14
Reset Value
0x00000000
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30
↑
ZP15
37