Xilinx MicroBlaze Reference Manual page 124

Chapter 3: MicroBlaze Signal Interface Description
ICACHE_FSL_IN_Data
ICACHE_FSL_IN_Control
ICACHE_FSL_IN_Exists
ICACHE_FSL_OUT_Clk
ICACHE_FSL_OUT_Write
ICACHE_FSL_OUT_Data
ICACHE_FSL_OUT_Control
ICACHE_FSL_OUT_Full
DCACHE_FSL_IN_Clk
DCACHE_FSL_IN_Read
DCACHE_FSL_IN_Data
DCACHE_FSL_IN_Control
DCACHE_FSL_IN_Exists
DCACHE_FSL_OUT_Clk
DCACHE_FSL_OUT_Write
DCACHE_FSL_OUT_Data
124
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Table 3-12: MicroBlaze Cache Link Signals (Continued)
Signal Name
Read data from I-side return
read data FSL
FSL control-bit from I-side
return read data FSL.
Reserved for future use
More read data exists in I-side
return FSL
Clock output to I-side read
access FSL
Write new cache miss access
request to I-side read access
FSL
Cache miss access (=address)
to I-side read access FSL
FSL control-bit to I-side read
access FSL. Reserved for
future use
FSL access buffer for I-side
read accesses is full
Clock output to D-side return
read data FSL
Read signal to D-side return
read data FSL
Read data from D-side return
read data FSL
FSL control bit from D-side
return read data FSL
More read data exists in D-
side return FSL
Clock output to D-side read
access FSL
Write new cache miss access
request to D-side read access
FSL
Cache miss access (read
address or write address +
write data + byte write enable
+ burst write encoding) to D-
side read access FSL
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Description VHDL Type
std_logic_
vector (0 to 31)
std_logic
std_logic
std_logic
std_logic
std_logic_
vector (0 to 31)
std_logic
std_logic
std_logic
std_logic
std_logic_
vector (0 to 31)
std_logic
std_logic
std_logic
std_logic
std_logic_
vector (0 to 31)
MicroBlaze Processor Reference Guide
Direction
input
input
input
output
output
output
output
input
output
output
input
input
input
output
output
output
UG081 (v14.7)