Xilinx MicroBlaze Reference Manual page 107

Table 3-1: Summary of MicroBlaze Core I/O (Continued)
Reset
MB_Reset
Clk
Ext_BRK
Ext_NM_BRK
MB_Halted
Dbg_Stop
MB_Error
Sleep
Wakeup[0:1]
Dbg_Wakeup
Lockstep_...
Dbg_...
Trace_...
1. Only used with C_USE_INTERRUPT = 2, for low-latency interrupt support.
2. The Reset and MB_Reset signals are functionally equivalent. MB_Reset is intended for the AXI4 and PLB
3. MicroBlaze is a synchronous design clocked with the Clk signal, except for hardware debug logic, which is
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Signal
2
2
interfaces.
clocked with the Dbg_Clk signal. If hardware debug logic is not used, there is no minimum frequency limit for
Clk. However, if hardware debug logic is used, there are signals transferred between the two clock regions. In this
case Clk must have a higher frequency than Dbg_Clk.
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Interface I/O
Core I Core reset, active high. Should be held for at
least 1 Clk clock cycle.
Core I Core reset, active high. Should be held for at
least 1 Clk clock cycle.
3
Core I Clock
Core I Break signal from MDM
Core I Non-maskable break signal from MDM
Core O Pipeline is halted, either via the Debug
Interface or by setting Dbg_Stop
I Unconditionally force pipeline to halt as
Core
soon as possible. Rising-edge detected pulse
that should be held for at least 1 Clk clock
cycle. The signal only has any effect when
C_DEBUG_ENABLED is set to 1.
O Pipeline is halted due to a missed exception,
Core
when C_FAULT_TOLERANT is set to 1.
O MicroBlaze is in sleep mode after executing
Core
a SLEEP instruction, all external accesses
are completed, and the pipeline is halted.
Core I Wake MicroBlaze from sleep mode when
either or both bits are set to 1. Ignored if
MicroBlaze is not in sleep mode.
Core O Debug request that external logic should
wake MicroBlaze from sleep mode with the
Wakeup signal.
Core IO Lockstep signals for high integrity
applications. See
Core IO Debug signals from MDM. See
for details.
Core O Trace signals for real time HW analysis. See
Table 3-16
MicroBlaze I/O Overview
Description
Table 3-13 for details.
Table 3-15
for details.
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