Xilinx MicroBlaze Reference Manual page 33

Table 2-12: Exception Specific Status (ESS) (Continued)
Instruction
storage
Data TLB
miss
Instruction
TLB miss
Branch Target Register (BTR)
The Branch Target Register only exists if the MicroBlaze processor is configured to use exceptions.
The register stores the branch target address for all delay slot branch instructions executed while
MSR[EIP] = 0. If an exception is caused by an instruction in a delay slot (that is, ESR[DS]=1), the
exception handler should return execution to the address stored in BTR instead of the normal
exception return address stored in R17. When read with the MFS instruction, the BTR is specified
by setting Sa = 0x000B. The BTR register is illustrated in
descriptions and reset values.
0
Table 2-13: Branch Target Register (BTR)
0:31
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Exception
Bits
Cause
20 DIZ
21:26 Reserved
20 Reserved
21 S
22:26 Reserved
20:26 Reserved
Figure 2-7: BTR
Bits Name
BTR Branch target address used by handler when
returning from an exception caused by an
instruction in a delay slot.
Read-only
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Name Description
Instruction storage - Zone protection
0 = Did not occur
1 = Occurred
Data TLB miss - Store instruction
0 = Did not occur
1 = Occurred
Figure 2-7
↑
BTR
Description
Registers
Reset Value
0
0
0
0
0
0
and Table 2-13 provides bit
31
Reset Value
0x00000000
33
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