Xilinx MicroBlaze Reference Manual page 142

Chapter 3: MicroBlaze Signal Interface Description
Table 3-18: MPD Parameters (Continued)
Parameter Name
C_ICACHE_ALWAYS_USED
C_ICACHE_INTERFACE
C_ICACHE_FORCE_TAG_LUTRAM
C_ICACHE_STREAMS
C_ICACHE_VICTIMS
C_ICACHE_DATA_WIDTH
C_ADDR_TAG_BITS
C_CACHE_BYTE_SIZE
C_ICACHE_USE_FSL
C_DCACHE_BASEADDR
C_DCACHE_HIGHADDR
C_USE_DCACHE
C_ALLOW_DCACHE_WR
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Feature/Description
Instruction cache interface
used for all memory
accesses in the cacheable
range
Instruction cache
CacheLink interface
protocol
0 = IXCL
1 = IXCL2
Instruction cache tag
always implemented with
distributed RAM
Instruction cache streams
Instruction cache victims
Instruction cache data
width
0 = 32 bits
1 = Full cache line
2 = 512 bits
Instruction cache address
tags
Instruction cache size
Cache over CacheLink
instead of peripheral bus
for instructions
Data cache base address
Data cache high address
Data cache
Data cache write enable
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EDK
Allowable Default Tool
Values Value Assig
ned
0, 1 0
0, 1 0 yes
0, 1 0
0, 1 0
0, 2, 4, 8 0
0, 1, 2 0
0-25 17
64, 128, 256,
512, 1024,
2048, 4096,
8192
8192, 16384,
32768,
4
65536
1 1
0x00000000 - 0x0000
0xFFFFFFFF 0000
0x00000000 - 0x3FFF
0xFFFFFFFF FFFF
0, 1 0
0, 1 1
MicroBlaze Processor Reference Guide
VHDL Type
integer
integer
3
integer
integer
integer
integer
yes integer
integer
integer
std_logic_vector
std_logic_vector
integer
integer
UG081 (v14.7)