Xilinx MicroBlaze Reference Manual page 164

Chapter 5: MicroBlaze Instruction Set Architecture
and
Logical AND
and
1 0 0 0 0 1
0 6
Description
The contents of register rA are ANDed with the contents of register rB; the result is placed into
register rD.
Pseudocode
Registers Altered
•
Latency
1 cycle
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rD, rA, rB
rD rA
1
1
← (rA) ∧ (rB)
(rD)
rD
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rB 0 0 0 0 0 0 0 0 0 0 0
1 2
6 1
MicroBlaze Processor Reference Guide
3
1
UG081 (v14.7)