Xilinx MicroBlaze Reference Manual page 119

Read and Write Data Steering
The MicroBlaze data-side bus interface performs the read steering and write steering required to
support the following transfers:
•
•
•
MicroBlaze does not support transfers that are larger than the addressed device. These types of
transfers require dynamic bus sizing and conversion cycles that are not supported by the MicroBlaze
bus interface. Data steering for read cycles are shown in
for write cycles are shown in
Table 3-6: Big Endian Read Data Steering (Load to Register rD)
Table 3-7: Little Endian Read Data Steering (Load to Register rD)
MicroBlaze Processor Reference Guide
UG081 (v14.7)
byte, halfword, and word transfers to word devices
byte and halfword transfers to halfword devices
byte transfers to byte devices
Table 3-8
Address Byte_Enable
[30:31] [0:3]
11 0001
10 0010
01 0100
00 1000
10 0011
00 1100
00 1111
Address Byte_Enable
[30:31] [0:3]
11 1000
10 0100
01 0010
00 0001
10 1100
00 0011
00 1111
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Local Memory Bus (LMB) Interface Description
Table 3-6
and Table 3-9.
Transfer
Size
rD[0:7] rD[8:15]
byte
byte
byte
byte
halfword
halfword
word Byte0
Transfer
Size
rD[0:7] rD[8:15]
byte
byte
byte
byte
halfword
halfword
word Byte0
and Table 3-7, and data steering
Register rD Data
rD[16:23] rD[24:31]
Byte3
Byte2
Byte1
Byte0
Byte2 Byte3
Byte0 Byte1
Byte1 Byte2 Byte3
Register rD Data
rD[16:23] rD[24:31]
Byte0
Byte1
Byte2
Byte3
Byte0 Byte1
Byte2 Byte3
Byte1 Byte2 Byte3
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