Xilinx MicroBlaze Reference Manual page 18

Chapter 2: MicroBlaze Architecture
Table 2-6: MicroBlaze Instruction Set Summary (Continued)
Type A
Type B
TNCAPUT Ra,FSLx
OR Rd,Ra,Rb
AND Rd,Ra,Rb
XOR Rd,Ra,Rb
ANDN Rd,Ra,Rb
PCMPBF Rd,Ra,Rb
PCMPEQ Rd,Ra,Rb
PCMPNE Rd,Ra,Rb
SRA Rd,Ra
SRC Rd,Ra
SRL Rd,Ra
SEXT8 Rd,Ra
SEXT16 Rd,Ra
CLZ Rd, Ra
SWAPB Rd, Ra
SWAPH Rd, Ra
WIC Ra,Rb
WDC Ra,Rb
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0-5 6-10 11-15 16-20
0-5 6-10 11-15
011011 00000 Ra
100000 Rd Ra
100001 Rd Ra
100010 Rd Ra
100011 Rd Ra
100000 Rd Ra
100010 Rd Ra
100011 Rd Ra
100100 Rd Ra
100100 Rd Ra
100100 Rd Ra
100100 Rd Ra
100100 Rd Ra
100100 Rd Ra
100100 Rd Ra
100100 Rd Ra
100100 00000 Ra
100100 00000 Ra
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21-31
16-31
1N1TA0000000 & FSLx := Ra (control write, blocking if N = 0)
FSLx MSR[C] := FSLx_M_Full if N = 1
Rb 00000000000 Rd := Ra or Rb
Rb 00000000000 Rd := Ra and Rb
Rb 00000000000 Rd := Ra xor Rb
Rb 00000000000 Rd := Ra and Rb
Rb 10000000000 Rd := 1 if (Rb[0:7] = Ra[0:7]) else
Rd := 2 if (Rb[8:15] = Ra[8:15]) else
Rd := 3 if (Rb[16:23] = Ra[16:23]) else
Rd := 4 if (Rb[24:31] = Ra[24:31]) else
Rd := 0
Rb 10000000000 Rd := 1 if (Rd = Ra) else
Rd := 0
Rb 10000000000 Rd := 1 if (Rd != Ra) else
Rd := 0
0000000000000001 Rd := s(Ra >> 1)
C := Ra[31]
0000000000100001 Rd := C & (Ra >> 1)
C := Ra[31]
0000000001000001 Rd := 0 & (Ra >> 1)
C := Ra[31]
0000000001100000 Rd := s(Ra[24:31])
0000000001100001 Rd := s(Ra[16:31])
0000000011100000 Rd = clz(Ra)
0000000111100000 Rd = (Ra)[24:31, 16:23, 8:15, 0:7]
0000000111100010 Rd = (Ra)[16:31, 0:15]
Rb 00001101000 ICache_Line[Ra >> 4].Tag := 0 if
(C_ICACHE_LINE_LEN = 4)
ICache_Line[Ra >> 5].Tag := 0 if
(C_ICACHE_LINE_LEN = 8)
Rb 00001100100 Cache line is cleared, discarding stored data.
DCache_Line[Ra >> 4].Tag := 0 if
(C_DCACHE_LINE_LEN = 4)
DCache_Line[Ra >> 5].Tag := 0 if
(C_DCACHE_LINE_LEN = 8)
MicroBlaze Processor Reference Guide
Semantics
UG081 (v14.7)