Xilinx MicroBlaze Reference Manual page 32

Chapter 2: MicroBlaze Architecture
Table 2-12: Exception Specific Status (ESS)
Unaligned
Data Access
Illegal
Instruction
Instruction
bus error
Data bus
error
Divide
Floating
point unit
Privileged
instruction
Stack
protection
violation
Stream
Data storage
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Exception
Bits
Cause
20 W
21 S
22:26 Rx
20:26 Reserved
20 ECC
21:26 Reserved
20 ECC
21:26 Reserved
20 DEC
21:26 Reserved
20:26 Reserved
20:26 Reserved
20:26 Reserved
20:22 Reserved
23:26 FSL
20 DIZ
21 S
22:26 Reserved
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Name Description
Word Access Exception
0 = unaligned halfword access
1 = unaligned word access
Store Access Exception
0 = unaligned load access
1 = unaligned store access
Source/Destination Register
General purpose register used as
source (Store) or destination (Load)
in unaligned access
Exception caused by ILMB
correctable or uncorrectable error
Exception caused by DLMB
correctable or uncorrectable error
Divide - Division exception cause
0 = Divide-By-Zero
1 = Division Overflow
Stream (FSL or AXI) index that
caused the exception
Data storage - Zone protection
0 = Did not occur
1 = Occurred
Data storage - Store instruction
0 = Did not occur
1 = Occurred
MicroBlaze Processor Reference Guide
Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
UG081 (v14.7)