Xilinx MicroBlaze Reference Manual page 143

Table 3-18: MPD Parameters (Continued)
Parameter Name
C_DCACHE_LINE_LEN
C_DCACHE_ALWAYS_USED
C_DCACHE_INTERFACE
C_DCACHE_FORCE_TAG_LUTRAM
C_DCACHE_USE_WRITEBACK
C_DCACHE_VICTIMS
C_DCACHE_DATA_WIDTH
C_DCACHE_ADDR_TAG
C_DCACHE_BYTE_SIZE
C_DCACHE_USE_FSL
C_DPLB_DWIDTH
C_DPLB_NATIVE_DWIDTH
C_DPLB_BURST_EN
C_DPLB_P2P
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Feature/Description
Data cache line length
Data cache interface used
for all accesses in the
cacheable range
Data cache CacheLink
interface protocol
0 = DXCL
1 = DXCL2
Data cache tag always
implemented with
distributed RAM
Data cache write-back
storage policy used
Data cache victims
Data cache data width
0 = 32 bits
1 = Full cache line
2 = 512 bits
Data cache address tags
Data cache size
Cache over CacheLink
instead of peripheral bus
for data
Data side PLB data width
Data side PLB native data
width
Data side PLB burst enable
Data side PLB Point-to-
point
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MicroBlaze Core Configurability
EDK
Allowable Default Tool
Values Value Assig
ned
4, 8 4
0, 1 0
0, 1 0 yes
0, 1 0
0, 1 0
0, 2, 4, 8 0
0, 1, 2 0
0-25 17
64, 128, 256,
512, 1024,
2048, 4096,
8192
8192, 16384,
32768,
4
65536
1 1
32 32
32 32
0 0
0, 1 0
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VHDL Type
integer
integer
integer
3
integer
integer
integer
integer
yes integer
integer
integer
integer
integer
integer
integer
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