Xilinx MicroBlaze Reference Manual page 209

lw
Load Word
lw
lwr
1 1 0 0 1 0
0 6
Description
Loads a word (32 bits) from the word aligned memory location that results from adding the contents
of registers rA and rB. The data is placed in register rD.
If the R bit is set, the bytes in the loaded word are reversed , loading data with the opposite
endianness of the endianness defined by C_ENDIANNESS and the E bit (if virtual protected mode
is enabled).
A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry
corresponding to the address is not found in the TLB.
A data storage exception occurs if access is prevented by a no-access-allowed zone protection. This
only applies to accesses with user mode and virtual protected mode enabled.
An unaligned data access exception occurs if the two least significant bits in the address are not zero.
Pseudocode
Registers Altered
•
•
•
•
•
Latency
•
•
Note
The word reversed instruction is only valid if MicroBlaze is configured to use reorder instructions
(C_USE_REORDER_INSTR = 1).
MicroBlaze Processor Reference Guide
UG081 (v14.7)
rD, rA, rB
rD, rA, rB
rD rA
11
←
Addr (rA) + (rB)
if TLB_Miss(Addr) and MSR[VM] = 1 then
←
ESR[EC] 10010;ESR[S]
←
MSR[UMS] MSR[UM]; MSR[VMS]
else if Access_Protected(Addr) and MSR[UM] = 1 and MSR[VM] = 1 then
←
ESR[EC] 10000;ESR[S]
←
MSR[UMS] MSR[UM]; MSR[VMS]
≠
else if Addr[30:31]
←
ESR[EC] 00001; ESR[W]
else
←
(rD) Mem(Addr)
rD, unless an exception is generated, in which case the register is unchanged
MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage
exception is generated
ESR[EC], ESR[S], if an exception is generated
ESR[DIZ], if a data storage exception is generated
ESR[W], ESR[Rx], if an unaligned data access exception is generated
1 cycle with C_AREA_OPTIMIZED=0
2 cycles with C_AREA_OPTIMIZED=1
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rB 0 R 0 0 0 0 0 0 0 0 0
16 21
←
0
←
MSR[VM]; MSR[UM]
← ←
0; ESR[DIZ] 1
←
MSR[VM]; MSR[UM]
0 then
← ←
1; ESR[S] 0; ESR[Rx]
Instructions
31
← ←
0; MSR[VM] 0
← ←
0; MSR[VM] 0
←
rD
209
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