Xilinx MicroBlaze Reference Manual page 89

The self-test example can be found in the standalone BSP BRAM driver source code, typically in the
subdirectory
Scrubbing
Scrubbing Methods
Scrubbing is performed using specific methods for the different block RAMs:
•
•
•
•
It is also possible to add interrupts for correctable errors from the LMB BRAM Interface
Controllers, and immediately scrub this address in the interrupt handler, although in most cases it
only improves reliability slightly.
The failing address can be determined by reading the Correctable Error First Failing Address
Register in each of the LMB BRAM Interface Controllers. To be able to generate an interrupt
C_ECC_STATUS_REGISTERS must be set to 1 in the connected LMB BRAM Interface
Controllers, and to read the failing address C_CE_FAILING_REGISTERS must be set to 1.
Calculating Scrubbing Rate
The scrubbing rate depends on failure intensity and desired reliability.
The approximate equation to determine the LMB memory scrubbing rate is in our case given by
where P
for a single memory bit, and SR is the Scrubbing Rate.
The soft error rates affecting block RAM for each product family can be found in
Report
Use Cases
Several common use cases are described here. These use cases are derived from the
Processor LMB BRAM Interface Controller (PG061)
Minimal
This system is obtained when enabling fault tolerance in MicroBlaze, without doing any other
configuration.
The system is suitable when area constraints are high, and there is no need for testing of the ECC
function, or analysis of error frequency and location. No ECC registers are implemented. Single bit
errors are corrected by the ECC logic before being passed to MicroBlaze. Uncorrectable errors set
an error signal, which generates an exception in MicroBlaze.
MicroBlaze Processor Reference Guide
UG081 (v14.7)
microblaze_0/libsrc/bram_v3_00_a/src/xbram_selftest.c
Instruction and data caches: All lines in the caches are cyclically invalidated using the WIC
and WDC instructions respectively. This forces the cache to reload the cache line from external
memory.
Memory Management Unit UTLB: All entries in the UTLB are cyclically invalidated by
writing the TLBHI register with the valid bit cleared.
Branch Target Cache: The entire BTC is invalided by doing a synchronizing branch, BRI 4.
LMB block RAM: All addresses in the memory are cyclically read and written, thus correcting
any single bit errors on each address.
 2 
BER
P ≈ 760  ----------- - 
W
2
 
SR
is the probability of an uncorrectable error in a memory word, BER is the soft error rate
W
(UG116).
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Fault Tolerance
Device Reliability
product guide.
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