Xilinx MicroBlaze Reference Manual page 77

Table 2-39: AXI4 Data Cache Interface Accesses (Continued)
Write-back
Table 2-40: CacheLink Data Cache Interface Accesses
Write-through
Write-back
Victim Cache
The victim cache is enabled by setting the parameter C_DCACHE_VICTIMS to 2, 4 or 8. This
defines the number of cache lines that can be stored in the victim cache. Whenever a complete cache
line is evicted from the cache, it is saved in the victim cache. By saving the most recent lines they
can be fetched much faster, should the processor request them, thereby improving performance. If
the victim cache is not used, all evicted cache lines must be read from memory again when they are
needed.
With the AXI4 interface, C_DCACHE_DATA_WIDTH determines the amount of data transferred
from/to the victim cache each clock cycle, either 32 bits or an entire cache line.
Note that to be able to use the victim cache, write-back must be enabled and area optimization must
not be enabled.
Data Cache Software Support
MSR Bit
The DCE bit in the MSR controls whether or not the cache is enabled. When disabling caches the
user must ensure that all the prior writes within the cacheable range have been completed in external
memory before reading back over M_AXI_DP or PLB. This can be done by writing to a semaphore
immediately before turning off caches, and then in a loop poll until it has been written.
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Policy State Direction
Cache
Enabled
Write
Cache
Disabled
Write
Policy State Direction
Cache
Enabled
Write
Cache
Disabled
Write
Cache
Enabled
Write
Cache
Disabled
Write
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Read Burst for 32-bit interface, single access otherwise
Burst for 32-bit interface cache lines with more than
one valid word, a single access otherwise
Read Burst for 32-bit interface non-exclusive access,
discarding all but the desired data, a single access
otherwise
Single access
Read Burst access
Single access
Read Burst access discarding all but the desire data
Single access
Read Burst access
Burst for complete valid cache lines, one or more
single accesses otherwise
Read Burst for 32-bit interface discarding all but the desired
data, single access otherwise
Single access
Data Cache
Access Type
Access Type
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