Xilinx MicroBlaze Reference Manual page 239

rted
Return from Exception
rted
1 0 1 1 0 1 1 0 1 0 0
0 6
Description
Return from exception will branch to the location specified by the contents of rA plus the IMM field,
sign-extended to 32 bits. The instruction will also enable exceptions after execution.
This instruction always has a delay slot. The instruction following the RTED is always executed
before the branch target.
When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged.
This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction
exception occurs.
Pseudocode
Registers Altered
•
•
•
Latency
•
Note
Convention is to use general purpose register r17 as rA. This instruction requires that one or more of
the MicroBlaze parameters C_*_EXCEPTION are set to 1 or that C_USE_MMU > 0.
A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and
external hardware breaks are deferred until after the delay slot branch has been completed.
The instruction should normally not be used when MSR[EE] is set, since if the instruction in the
delay slot would cause an exception, the exception handler would be entered with exceptions
enabled.
Note:
to the address in BTR.
MicroBlaze Processor Reference Guide
UG081 (v14.7)
rA, IMM
rA
11
if MSR[UM] = 1 then
←
ESR[EC] 00111
else
←
(rA) + sext(IMM)
PC
allow following instruction to complete execution
←
MSR[EE] 1
←
MSR[EIP] 0
←
MSR[UM] MSR[UMS]
←
MSR[VM] MSR[VMS]
← 0
ESR
PC
MSR[EE], MSR[EIP], MSR[UM], MSR[VM]
ESR
2 cycles
Code returning from an exception must first check if MSR[DS] is set, and in that case return
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IMM
16
Instructions
31
239
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