Xilinx MicroBlaze Reference Manual page 19

Table 2-6: MicroBlaze Instruction Set Summary (Continued)
Type A
Type B
WDC.FLUSH Ra,Rb
WDC.CLEAR Ra,Rb
MBAR Imm
MTS Sd,Ra
MFS Rd,Sa
MSRCLR Rd,Imm
MSRSET Rd,Imm
BR Rb
BRD Rb
MicroBlaze Processor Reference Guide
UG081 (v14.7)
0-5 6-10 11-15 16-20
0-5 6-10 11-15
100100 00000 Ra
100100 00000 Ra
101110 Imm 00010
100101 00000 Ra
100101 Rd 00000
100101 Rd 00001
100101 Rd 00000
100110 00000 00000
100110 00000 10000
www.xilinx.com
21-31
16-31
Rb 00001110100 Cache line is flushed, writing stored data to
memory, and then cleared. Used when
C_DCACHE_USE_WRITEBACK = 1.
Rb 00001110110 Cache line with matching address is cleared,
discarding stored data. Used when
C_DCACHE_USE_WRITEBACK = 1.
0000000000000100 PC := PC + 4; Wait for memory accesses.
11 & Sd SPR[Sd] := Ra, where:
• SPR[0x0001] is MSR
• SPR[0x0007] is FSR
• SPR[0x0800] is SLR
• SPR[0x0802] is SHR
• SPR[0x1000] is PID
• SPR[0x1001] is ZPR
• SPR[0x1002] is TLBX
• SPR[0x1003] is TLBLO
• SPR[0x1004] is TLBHI
• SPR[0x1005] is TLBSX
10 & Sa Rd := SPR[Sa], where:
• SPR[0x0000] is PC
• SPR[0x0001] is MSR
• SPR[0x0003] is EAR
• SPR[0x0005] is ESR
• SPR[0x0007] is FSR
• SPR[0x000B] is BTR
• SPR[0x000D] is EDR
• SPR[0x0800] is SLR
• SPR[0x0802] is SHR
• SPR[0x1000] is PID
• SPR[0x1001] is ZPR
• SPR[0x1002] is TLBX
• SPR[0x1003] is TLBLO
• SPR[0x1004] is TLBHI
• SPR[0x2000 to 0x200B] is PVR[0 to 12]
00 & Imm14 Rd := MSR
MSR := MSR and Imm14
00 & Imm14 Rd := MSR
MSR := MSR or Imm14
Rb 00000000000 PC := PC + Rb
Rb 00000000000 PC := PC + Rb
Instructions
Semantics
19
Send Feedback