Xilinx MicroBlaze Reference Manual page 163

addi
Arithmetic Add Immediate
addi
addic
addik
addikc
0 0 1 K C 0
0 6
Description
The sum of the contents of registers rA and the value in the IMM field, sign-extended to 32 bits, is
placed into register rD. Bit 3 of the instruction (labeled as K in the figure) is set to one for the
mnemonic addik. Bit 4 of the instruction (labeled as C in the figure) is set to one for the mnemonic
addic. Both bits are set to one for the mnemonic addikc.
When an addi instruction has bit 3 set (addik, addikc), the carry flag will keep its previous value
regardless of the outcome of the execution of the instruction. If bit 3 is cleared (addi, addic), then the
carry flag will be affected by the execution of the instruction.
When bit 4 of the instruction is set to one (addic, addikc), the content of the carry flag (MSR[C])
affects the execution of the instruction. When bit 4 is cleared (addi, addik), the content of the carry
flag does not affect the execution of the instruction (providing a normal addition).
Pseudocode
Registers Altered
•
•
Latency
1 cycle
Notes
The C bit in the instruction opcode is not the same as the carry bit in the MSR.
By default, Type B Instructions take the 16-bit IMM field value and sign extend it to 32 bits to use
as the immediate operand. This behavior can be overridden by preceding the Type B instruction with
an imm instruction. See the instruction
values.
MicroBlaze Processor Reference Guide
UG081 (v14.7)
rD, rA, IMM
rD, rA, IMM
rD, rA, IMM
rD, rA, IMM
rD rA
1
1
if C = 0 then
←
(rD) (rA) + sext(IMM)
else
←
(rD) (rA) + sext(IMM) + MSR[C]
if K = 0 then
←
MSR[C] CarryOut
rD
MSR[C]
www.xilinx.com
Add Immediate
Add Immediate with Carry
Add Immediate and Keep Carry
Add Immediate with Carry and Keep Carry
IMM
1
6
"imm," page 204 for details on using 32-bit immediate
Instructions
3
1
163
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