Xilinx MicroBlaze Reference Manual page 249

srl
Shift Right Logical
srl
1 0 0 1 0 0
0 6
Description
Shifts logically the contents of register rA, one bit to the right, and places the result in rD. A zero is
shifted in the shift chain and placed in the most significant bit of rD. The least significant bit coming
out of the shift chain is placed in the Carry flag.
Pseudocode
Registers Altered
•
•
Latency
•
MicroBlaze Processor Reference Guide
UG081 (v14.7)
rD, rA
rD rA
1
1
←
(rD)[0] 0
← (
(rD)[1:31] rA)[0:30]
←
MSR[C] (rA)[31]
rD
MSR[C]
1 cycle
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0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1
1
6
Instructions
3
1
249
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