Instruction Cache - Xilinx MicroBlaze Reference Manual

Chapter 2: MicroBlaze Architecture

Instruction Cache

Overview
MicroBlaze can be used with an optional instruction cache for improved performance when
executing code that resides outside the LMB address range.
The instruction cache has the following features:
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General Instruction Cache Functionality
When the instruction cache is used, the memory address space is split into two segments: a
cacheable segment and a non-cacheable segment. The cacheable segment is determined by two
parameters: C_ICACHE_BASEADDR and C_ICACHE_HIGHADDR. All addresses within this
range correspond to the cacheable address segment. All other addresses are non-cacheable.
The cacheable segment size must be 2
C_ICACHE_BASEADDR and C_ICACHE_HIGHADDR must comprise a complete power-of-two
range, such that range = 2
zero.
The cacheable instruction address consists of two parts: the cache address, and the tag address. The
MicroBlaze instruction cache can be configured from 64 bytes to 64 kB. This corresponds to a cache
address of between 6 and 16 bits. The tag address together with the cache address should match the
full address of cacheable memory. When selecting cache sizes below 2 kB, distributed RAM is used
to implement the Tag RAM and Instruction RAM. Distributed RAM is always used to implement
the Tag RAM, when setting the parameter C_ICACHE_FORCE_TAG_LUTRAM to 1. This
parameter is only available with cache sizes 8 kB or 16 kB and less, for 4 or 8 word cache-lines,
respectively.
For example: in a MicroBlaze configured with C_ICACHE_BASEADDR= 0x00300000,
C_ICACHE_HIGHADDR=0x0030ffff, C_CACHE_BYTE_SIZE=4096,
C_ICACHE_LINE_LEN=8, and C_ICACHE_FORCE_TAG_LUTRAM=0; the cacheable memory
of 64 kB uses 16 bits of byte address, and the 4 kB cache uses 12 bits of byte address, thus the
required address tag width is: 16-12=4 bits. The total number of block RAM primitives required in
this configuration is: 2 RAMB16 for storing the 1024 instruction words, and 1 RAMB16 for 128
cache line entries, each consisting of: 4 bits of tag, 8 word-valid bits, 1 line-valid bit. In total 3
RAMB16 primitives.
Figure 2-22, page 74
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Direct mapped (1-way associative)
User selectable cacheable memory address range
Configurable cache and tag size
Caching over AXI4 interface (M_AXI_IC) or CacheLink (XCL) interface
Option to use 4 or 8 word cache-line
Cache on and off controlled using a bit in the MSR
Optional WIC instruction to invalidate instruction cache lines
Optional stream buffers to improve performance by speculatively prefetching instructions
Optional victim cache to improve performance by saving evicted cache lines
Optional parity protection that invalidates cache lines if a Block RAM bit error is detected
Optional data width selection to either use 32 bits, an entire cache line, or 512 bits
N
and the N least significant bits of C_ICACHE_BASEADDR must be
shows the organization of Instruction Cache.
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N
, where N is a positive integer. The range specified by
MicroBlaze Processor Reference Guide
UG081 (v14.7)