Xilinx MicroBlaze Reference Manual page 22

Chapter 2: MicroBlaze Architecture
Table 2-6: MicroBlaze Instruction Set Summary (Continued)
Type A
Type B
SB Rd,Ra,Rb
SBR Rd,Ra,Rb
SH Rd,Ra,Rb
SHR Rd,Ra,Rb
SW Rd,Ra,Rb
SWR Rd,Ra,Rb
SWX Rd,Ra,Rb
LBUI Rd,Ra,Imm
LHUI Rd,Ra,Imm
LWI Rd,Ra,Imm
SBI Rd,Ra,Imm
SHI Rd,Ra,Imm
SWI Rd,Ra,Imm
1. Due to the many different corner cases involved in floating point arithmetic, only the normal behavior is described. A full description of the
behavior can be found in Chapter 5, "MicroBlaze Instruction Set Architecture."
Semaphore Synchronization
The LWX and SWX. instructions are used to implement common semaphore operations, including
test and set, compare and swap, exchange memory, and fetch and add. They are also used to
implement spinlocks.
These instructions are typically used by system programs and are called by application programs as
needed. Generally, a program uses LWX to load a semaphore from memory, causing the reservation
to be set (the processor maintains the reservation internally). The program can compute a result
based on the semaphore value and conditionally store the result back to the same memory location
using the SWX instruction. The conditional store is performed based on the existence of the
reservation established by the preceding LWX instruction. If the reservation exists when the store is
executed, the store is performed and MSR[C] is cleared to 0. If the reservation does not exist when
the store is executed, the target memory location is not modified and MSR[C] is set to 1.
If the store is successful, the sequence of instructions from the semaphore load to the semaphore
store appear to be executed atomically—no other device modified the semaphore location between
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0-5 6-10 11-15 16-20
0-5 6-10 11-15
110100 Rd Ra
110101 Rd Ra
110110 Rd Ra
110110 Rd Ra
111000 Rd Ra
111001 Rd Ra
111010 Rd Ra
111100 Rd Ra
111101 Rd Ra
111110 Rd Ra
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21-31
16-31
Rb 00000000000 Addr := Ra + Rb
*Addr[0:8] := Rd[24:31]
01000000000
Rb 00000000000 Addr := Ra + Rb
*Addr[0:16] := Rd[16:31]
01000000000
Rb 00000000000 Addr := Ra + Rb
01000000000 *Addr := Rd
Rb 10000000000 Addr := Ra + Rb
*Addr := Rd if Reservation = 1
Reservation := 0
Imm Addr := Ra + s(Imm)
Rd[0:23] := 0
Rd[24:31] := *Addr[0:7]
Imm Addr := Ra + s(Imm)
Rd[0:15] := 0
Rd[16:31] := *Addr[0:15]
Imm Addr := Ra + s(Imm)
Rd := *Addr
Imm Addr := Ra + s(Imm)
*Addr[0:7] := Rd[24:31]
Imm Addr := Ra + s(Imm)
*Addr[0:15] := Rd[16:31]
Imm Addr := Ra + s(Imm)
*Addr := Rd
MicroBlaze Processor Reference Guide
Semantics
UG081 (v14.7)