Xilinx MicroBlaze Reference Manual page 202

Chapter 5: MicroBlaze Instruction Set Architecture
Pseudocode
Registers Altered
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Latency
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The blocking versions of this instruction will stall the pipeline of MicroBlaze until the instruction
can be completed. Interrupts are served unless the instruction is atomic, which ensures that the
instruction cannot be interrupted.
Note
The blocking versions of this instruction should not be placed in a delay slot, since this prevents
interrupts from being served.
For non-blocking versions, an rsubc instruction can be used to decrement an index variable.
The 'e' bit does not have any effect unless C_FSL_EXCEPTION is set to 1.
These instructions are only available when the MicroBlaze parameter C_FSL_LINKS is greater
than 0 and the parameter C_USE_EXTENDED_FSL_INSTR is set to 1.
It is not recommended to allow these instructions in user mode, unless absolutely necessary for
performance reasons, since that removes all hardware protection preventing incorrect use of a link.
202
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if MSR[UM] = 1 then
←
ESR[EC] 00111
else
←
x rB[28:31]
if x >= C_FSL_LINKS then
←
x 0
←
(rD) FSLx_S_DATA | Sx_AXIS_TDATA
if (n = 1) then
←
MSR[Carry] (FSLx_S_EXISTS | Sx_AXIS_TVALID)
if (FSLx_S_CONTROL | Sx_AXIS_TLAST
(FSLx_S_EXISTS | Sx_AXIS_TVALID) then
←
MSR[FSL] 1
if (e = 1) then
←
ESR[EC] 00000
←
ESR[ESS] rB[28:31]
←
EDR FSLx_S_DATA | Sx_AXIS_TDATA
rD, unless an exception is generated, in which case the register is unchanged
MSR[FSL]
MSR[Carry]
ESR[EC], in case a stream exception or a privileged instruction exception is generated
ESR[ESS], in case a stream exception is generated
EDR, in case a stream exception is generated
1 cycle with C_AREA_OPTIMIZED=0
2 cycles with C_AREA_OPTIMIZED=1
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MicroBlaze Processor Reference Guide
UG081 (v14.7)