Xilinx MicroBlaze Reference Manual page 180

Chapter 5: MicroBlaze Instruction Set Architecture
br
Unconditional Branch
br
bra
brd
brad
brld
brald
1 0 0 1 1 0
0 6
Description
Branch to the instruction located at address determined by rB.
The mnemonics brld and brald will set the L bit. If the L bit is set, linking will be performed. The
current value of PC will be stored in rD.
The mnemonics bra, brad and brald will set the A bit. If the A bit is set, it means that the branch is
to an absolute value and the target is the value in rB, otherwise, it is a relative branch and the target
will be PC + rB.
The mnemonics brd, brad, brld and brald will set the D bit. The D bit determines whether there is a
branch delay slot or not. If the D bit is set, it means that there is a delay slot and the instruction
following the branch (that is, in the branch delay slot) is allowed to complete execution before
executing the target instruction.
If the D bit is not set, it means that there is no delay slot, so the instruction to be executed after the
branch is the target instruction.
Pseudocode
Registers Altered
•
•
Latency
•
•
180
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rB
rB
rB
rB
rD, rB
rD, rB
rD D A L 0 0
1
1
if L = 1 then
←
(rD) PC
if A = 1 then
←
PC (rB)
else
←
PC PC + (rB)
if D = 1 then
allow following instruction to complete execution
rD
PC
2 cycles (if the D bit is set)
3 cycles (if the D bit is not set)
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Branch
Branch Absolute
Branch with Delay
Branch Absolute with Delay
Branch and Link with Delay
Branch Absolute and Link with Delay
rB 0 0 0 0 0 0 0 0 0 0 0
1 2
6 1
MicroBlaze Processor Reference Guide
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UG081 (v14.7)