Xilinx MicroBlaze Reference Manual page 223

mulhu
Multiply High Unsigned
mulhu
0 1 0 0 0 0
0 6
Description
Multiplies the contents of registers rA and rB and puts the result in register rD. This is a 32-bit by
32-bit unsigned multiplication that will produce a 64-bit unsigned result. The most significant word
of this value is placed in rD. The least significant word is discarded.
Pseudocode
Registers Altered
•
Latency
•
•
Note
This instruction is only valid if the target architecture has multiplier primitives, and if present, the
MicroBlaze parameter C_USE_HW_MUL is set to 2 (Mul64).
When MULHU is used, bit 30 and 31 in the MUL instruction must be zero to distinguish between
the two instructions. In previous versions of MicroBlaze, these bits were defined as zero, but the
actual values were not relevant.
MicroBlaze Processor Reference Guide
UG081 (v14.7)
rD, rA, rB
rD rA
1
1
← ×
(rD) MSW( (rA) (rB) ), unsigned
rD
1 cycle with C_AREA_OPTIMIZED=0
3 cycles with C_AREA_OPTIMIZED=1
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rB 0 0 0 0 0 0 0 0 0 1 1
1 2
6 1
Instructions
3
1
223
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