Xilinx MicroBlaze Reference Manual page 45

Table 2-25: Processor Version Register 1 (PVR1)
0:31
Table 2-26: Processor Version Register 2 (PVR2)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Bits Name
USR2 User configured value 2
Bits Name
DAXI Data side AXI4 or ACE in use C_D_AXI
DLMB Data side LMB in use
IAXI Instruction side AXI4 or ACE
in use
ILMB Instruction side LMB in use
IRQEDGE Interrupt is edge triggered
IRQPOS Interrupt edge is positive
DPLB Data side PLB in use
IPLB Instruction side PLB in use
INTERCON Use PLB interconnect
STREAM Use AXI4-Stream
interconnect
ACE Use ACE interconnect
AXI4DP Data Peripheral AXI interface
uses AXI4 protocol, with
support for exclusive access
FSL Use extended stream (FSL or
AXI) instructions
FSLEXC Generate exception for stream
control bit (FSL or AXI)
mismatch
MSR Use msrset and msrclr
instructions
PCMP Use pattern compare and CLZ
instructions
AREA Select implementation to
optimize area with lower
instruction throughput
BS Use barrel shifter
DIV Use divider
MUL Use hardware multiplier
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Description
C_PVR_USER2
Description
C_D_LMB
C_I_AXI
C_I_LMB
C_INTERRUPT_IS_EDGE
C_EDGE_IS_POSITIVE
C_D_PLB
C_I_PLB
C_INTERCONNECT = 1 (PLBv46)
C_STREAM_INTERCONNECT = 1
(AXI4-Stream)
C_INTERCONNECT = 3 (ACE)
C_M_AXI_DP_EXCLUSIVE_ACCESS
C_USE_EXTENDED_FSL_INSTR
C_FSL_EXCEPTION
C_USE_MSR_INSTR
C_USE_PCMP_INSTR
C_AREA_OPTIMIZED
C_USE_BARREL
C_USE_DIV
C_USE_HW_MUL > 0 (None)
Registers
Value
Value
45
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