Data Cache Read Miss - Xilinx MicroBlaze Reference Manual

Chapter 3: MicroBlaze Signal Interface Description
•
When the parameter C_DCACHE_USE_WRITEBACK is set to 1, write operations can store an
entire cache line using burst write, as well as single-words. Each cache line is always stored in linear
order, and the address output on the CacheLink is aligned to the cache line size. When the parameter
C_DCACHE_USE_WRITEBACK is cleared to 0, all write operations on the CacheLink are single-
word. C_DCACHE_INTERFACE must be set to 1 (DXCL2) when write-back is used, since burst
write is only available with the DXCL2 protocol.
Instruction Cache Read Miss
On a read miss the cache controller performs the following sequence:
1.
2.
Note:
at least one wait state must be used).
With the IXCL protocol (critical word first):
3.
4.
5.
With the IXCL2 protocol (linear fetch):
3.
4.
5.

Data Cache Read Miss

On a read miss the cache controller will perform the following sequence:
1.
2.
3.
Note:
at least one wait state must be used).
With the DXCL protocol (critical word first):
4.
5.
6.
1. Byte and halfword read misses are naturally expected to return complete words, the cache controller then provides the
126
Send Feedback
Linear fetch is used by the IXCL2 and DXCL2 protocol, selected when
C_ICACHE_INTERFACE = 1 (IXCL2) and C_DCACHE_INTERFACE = 1 (DXCL2),
respectively. The address output on the CacheLink is then aligned to the cache line size (that is,
if an access to address 0x348 is a miss with a 4 word cache line, then the address output on the
CacheLink is 0x340). The cache controller stores data in the cache memory, and forwards the
requested word to the execution unit when it is available.
(1)
Write the word aligned or cache line aligned missed address to ICACHE_FSL_OUT_Data,
with the control bit set low (ICACHE_FSL_OUT_Control = 0) to indicate a read access
Wait until ICACHE_FSL_IN_Exists goes high to indicate that data is available
There must be at least one clock cycle before ICACHE_FSL_IN_Exists goes high (
Store the word from ICACHE_FSL_IN_Data to the cache
Forward the critical word to the execution unit in order to resume execution
Repeat 3 and 4 for the subsequent 3 or 7 words in the cache line
Store words from ICACHE_FSL_IN_Data to the cache
Forward the relevant word to the execution unit in order to resume execution
Store remaining words from ICACHE_FSL_IN_Data to the cache
If DCACHE_FSL_OUT_Full = 1 then stall until it goes low
1
Write the word aligned or cache line aligned missed address to DCACHE_FSL_OUT_Data,
with the control bit set low (DCACHE_FSL_OUT_Control = 0) to indicate a read access
Wait until DCACHE_FSL_IN_Exists goes high to indicate that data is available
There must be at least one clock cycle before DCACHE_FSL_IN_Exists goes high (
Store the word from DCACHE_FSL_IN_Data to the cache
Forward the critical word to the execution unit in order to resume execution
Repeat 4 and 5 for the subsequent 3 or 7 words in the cache line
execution unit with the correct bytes.
www.xilinx.com MicroBlaze Processor Reference Guide
UG081 (v14.7)
that is
,
that is
,