Xilinx MicroBlaze Reference Manual page 58

Chapter 2: MicroBlaze Architecture
The MicroBlaze TLB is physically implemented as three separate TLBs:
•
•
•
Figure 2-19
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Unified TLB—The UTLB contains 64 entries and is pseudo-associative. Instruction-page and
data-page translation can be stored in any UTLB entry. The initialization and management of
the UTLB is controlled completely by software.
Instruction Shadow TLB—The ITLB contains instruction page-translation entries and is fully
associative. The page-translation entries stored in the ITLB represent the most-recently
accessed instruction-page translations from the UTLB. The ITLB is used to minimize
contention between instruction translation and UTLB-update operations. The initialization and
management of the ITLB is controlled completely by hardware and is transparent to software.
Data Shadow TLB—The DTLB contains data page-translation entries and is fully associative.
The page-translation entries stored in the DTLB represent the most-recently accessed data-
page translations from the UTLB. The DTLB is used to minimize contention between data
translation and UTLB-update operations. The initialization and management of the DTLB is
controlled completely by hardware and is transparent to software.
provides the translation flow for TLB.
Generate I-side
Effective Address
Translation Disabled Translation Enabled
(MSR[VM]=0) (MSR[VM]=1)
Perform ITLB
No Translation
ITLB Hit
Extract Real
Address from ITLB
Continue I-cache
Access
Extract Real
Address from UTLB
Route Address Route Address
to ITLB
Figure 2-19: TLB Address Translation Flow
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Translation Enabled
(MSR[VM]=1)
Perform DTLB
Look-Up
Look-Up
ITLB Miss DTLB Miss
Perform UTLB
Look-Up
UTLB Hit UTLB Miss
to DTLB
MicroBlaze Processor Reference Guide
Generate D-side
Effective Address
Translation Disabled
(MSR[VM]=0)
No Translation
DTLB Hit
Extract Real
Address from DTLB
Continue I-cache
or D-cache
Access
I-Side TLB Miss
or
D-Side TLB Miss
Exception
UG081 (v14.7)