Xilinx MicroBlaze Reference Manual page 215

The value read from FSR may not include effects of the immediately preceding instruction
(dependent on pipeline stall behavior). An instruction that does not affect FSR must precede the
MFS instruction to guarantee correct FSR value.
EAR, ESR and BTR are only valid as operands when at least one of the MicroBlaze
C_*_EXCEPTION parameters are set to 1.
EDR is only valid as operand when the parameter C_FSL_EXCEPTION is set to 1 and the
parameter C_FSL_LINKS is greater than 0.
FSR is only valid as an operand when the C_USE_FPU parameter is greater than 0.
SLR and SHR are only valid as an operand when the C_USE_STACK_PROTECTION parameter is
set to 1.
PID, ZPR, TLBLO and TLBHI are only valid as operands when the parameter C_USE_MMU > 1
(User Mode) and the parameter C_MMU_TLB_ACCESS = 1 (Read) or 3 (Full).
TLBX is only valid as operand when the parameter C_USE_MMU > 1 (User Mode) and the
parameter C_MMU_TLB_ACCESS > 0 (Minimal).
PVR0 is only valid as an operand when C_PVR is 1 (Basic) or 2 (Full), and PVR1 - PVR12 are only
valid as operands when C_PVR is set to 2 (Full).
MicroBlaze Processor Reference Guide
UG081 (v14.7)
www.xilinx.com
Instructions
215
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