Xilinx Cachelink (Xcl) Interface Description - Xilinx MicroBlaze Reference Manual

Xilinx CacheLink (XCL) Interface Description

Xilinx CacheLink (XCL) is a high performance solution for external memory accesses. The
MicroBlaze CacheLink interface is designed to connect directly to a memory controller with
integrated FSL buffers, for example, the MPMC. This method has the lowest latency and minimal
number of instantiations (see
The interface is only available on MicroBlaze when caches are enabled. It is legal to use a
CacheLink cache on the instruction side or the data side without caching the other.
How memory locations are accessed depend on the parameter C_ICACHE_ALWAYS_USED for the
instruction cache and the parameter C_DCACHE_ALWAYS_USED for the data cache. If the
parameter is 1, the cached memory range is always accessed via the CacheLink. If the parameter is
0, the cached memory range is accessed over PLB whenever the caches are software disabled (that
is, MSR[ICE]=0 or MSR[DCE]=0).
Memory locations outside the cacheable range are accessed over PLB or LMB.
The CacheLink cache controllers handle 4 or 8-word cache lines, either using critical word first or
linear fetch depending on the selected protocol. At the same time the separation from the PLB bus
reduces contention for non-cached memory accesses.
CacheLink Signal Interface
The CacheLink signals on MicroBlaze are listed in
ICACHE_FSL_IN_Clk
ICACHE_FSL_IN_Read
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Figure 3-10).
Schematic
Memory
Controller
MicroBlaze
Figure 3-10: CacheLink Connection with Integrated FSL Buffers
(Only Instruction Cache Used in this Example)
Table 3-12: MicroBlaze Cache Link Signals
Signal Name
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Xilinx CacheLink (XCL) Interface Description
Example MHS code
BEGIN microblaze
...
BUS_INTERFACE IXCL = myIXCL
...
END
BEGIN mpmc
...
BUS_INTERFACE XCL0 = myIXCL
...
END
Table 3-12.
Description
Clock output to I-side return
read data FSL
Read signal to I-side return
read data FSL.
VHDL Type Direction
std_logic output
std_logic output
123
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