Xilinx MicroBlaze Reference Manual page 260

Chapter 5: MicroBlaze Instruction Set Architecture
xori
Logical Exclusive OR with Immediate
xori
1 0 1 0 1 0
0 6
Description
The IMM field is extended to 32 bits by concatenating 16 0-bits on the left. The contents of register
rA are XOR'ed with the extended IMM field; the result is placed into register rD.
Pseudocode
Registers Altered
•
Latency
•
Note
By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to
use as the immediate operand. This behavior can be overridden by preceding the Type B instruction
with an imm instruction. See the instruction
values.
260
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rD, rA, IMM
rD rA
1
1
← ⊕
(rD) (rA) sext(IMM)
rD
1 cycle
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IMM
1
6
"imm," page 204 for details on using 32-bit immediate
MicroBlaze Processor Reference Guide
3
1
UG081 (v14.7)