Xilinx MicroBlaze Reference Manual page 106

Chapter 3: MicroBlaze Signal Interface Description
Table 3-1: Summary of MicroBlaze Core I/O (Continued)
IReady
IWait
ICE
IUE
Mn_AXIS_TLAST
Mn_AXIS_TDATA
Mn_AXIS_TVALID
Mn_AXIS_TREADY
Sn_AXIS_TLAST
Sn_AXIS_TDATA
Sn_AXIS_TVALID
Sn_AXIS_TREADY
FSL0_M .. FSL15_M
FSL0_S .. FSL15_S
ICache_FSL_in...
ICache_FSL_out...
DCache_FSL_in...
DCache_FSL_out...
Interrupt
Interrupt_Address
Interrupt_Ack
106
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Signal Interface
ILMB
ILMB
ILMB
ILMB
M0_AXIS..
M15_AXIS
M0_AXIS..
M15_AXIS
M0_AXIS..
M15_AXIS
M0_AXIS..
M15_AXIS
S0_AXIS..
S15_AXIS
S0_AXIS..
S15_AXIS
S0_AXIS..
S15_AXIS
S0_AXIS..
S15_AXIS
MFSL
or
DWFSL
SFSL
or
DRFSL
IXCL_S
IXCL_M
DXCL_S
DXCL_M
Core
1 Core
1 Core
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I/O Description
I Instruction interface LMB data ready
I Instruction interface LMB data wait
I Instruction interface LMB correctable error
I Instruction interface LMB uncorrectable
error
O Master interface output AXI4 channels
write last
O Master interface output AXI4 channels
write data
O Master interface output AXI4 channels
write valid
I Master interface input AXI4 channels
write ready
I Slave interface input AXI4 channels
write last
I Slave interface input AXI4 channels
write data
I Slave interface input AXI4 channels
write valid
O Slave interface output AXI4 channels
write ready
O Master interface to output FSL channels
MFSL is used for FSL bus connections,
whereas DWFSL is used for direct
connections with FSL slaves
I Slave interface to input FSL channels
SFSL is used for FSL bus connections,
whereas DRFSL is used for direct
connections with FSL masters
IO Instruction side CacheLink FSL slave
interface
IO Instruction side CacheLink FSL master
interface
IO Data side CacheLink FSL slave interface
IO Data side CacheLink FSL master interface
I Interrupt
I Interrupt vector address
O Interrupt acknowledge
MicroBlaze Processor Reference Guide
UG081 (v14.7)