Xilinx MicroBlaze Reference Manual page 46

Chapter 2: MicroBlaze Architecture
Table 2-26: Processor Version Register 2 (PVR2) (Continued)
20
21
22
23
24
25
26
27
28
29
30
31
Table 2-27: Processor Version Register 3 (PVR3)
0
1:2
3:6
7:9
10:12
13:15
16:18
19
46
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Bits Name
FPU Use FPU
MUL64 Use 64-bit hardware
multiplier
FPU2 Use floating point conversion
and square root instructions
IPLBEXC Generate exception for IPLB
error
DPLBEXC Generate exception for DPLB
error
OP0EXC Generate exception for 0x0
illegal opcode
UNEXC Generate exception for
unaligned data access
OPEXC Generate exception for any
illegal opcode
AXIIEXC Generate exception for
M_AXI_I error
AXIDEXC Generate exception for
M_AXI_D error
DIVEXC Generate exception for
division by zero or division
overflow
FPUEXC Generate exceptions from
FPU
Bits Name
DEBUG Use debug logic
Reserved
PCBRK Number of PC breakpoints
Reserved
RDADDR Number of read address
breakpoints
Reserved
WRADDR Number of write address
breakpoints
Reserved
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Description
C_USE_FPU > 0 (None)
C_USE_HW_MUL = 2 (Mul64)
C_USE_FPU = 2 (Extended)
C_IPLB_BUS_EXCEPTION
C_DPLB_BUS_EXCEPTION
C_OPCODE_0x0_ILLEGAL
C_UNALIGNED_EXCEPTIONS
C_ILL_OPCODE_EXCEPTION
C_M_AXI_I_BUS_EXCEPTION
C_M_AXI_D_BUS_EXCEPTION
C_DIV_ZERO_EXCEPTION
C_FPU_EXCEPTION
Description
C_DEBUG_ENABLED
C_NUMBER_OF_PC_BRK
C_NUMBER_OF_RD_ADDR_BRK
C_NUMBER_OF_WR_ADDR_BRK
MicroBlaze Processor Reference Guide
Value
Value
UG081 (v14.7)