Xilinx MicroBlaze Reference Manual page 183

Registers Altered
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Latency
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Notes
The instructions brli and brali are not available.
By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to
use as the immediate operand. This behavior can be overridden by preceding the Type B instruction
with an imm instruction. See the instruction
values.
A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and
external hardware breaks are deferred until after the delay slot branch has been completed.
MicroBlaze Processor Reference Guide
UG081 (v14.7)
rD
PC
MSR[UM], MSR[VM]
1 cycle (if successful branch prediction occurs)
2 cycles (if the D bit is set)
3 cycles (if the D bit is not set, or a branch prediction mispredict occurs)
www.xilinx.com
"imm," page 204 for details on using 32-bit immediate
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