Xilinx MicroBlaze Reference Manual page 127

With the DXCL2 protocol (linear fetch):
4.
5.
6.
Data Cache Write
When C_DCACHE_INTERFACE is set to 1 (DXCL2), the CacheLink can either do burst write or
single-word write.
A burst write is used when C_DCACHE_USE_WRITEBACK is set to 1 and an entire cache line is
valid. There are two occasions when an entire cache line becomes valid:
•
•
Note that writes to the data cache always are write-through when C_DCACHE_USE_WRITEBACK
is cleared to 0, and thus there is a write over the CacheLink regardless of whether there was a hit or
miss in the cache.
With the DXCL2 protocol, on a burst cache line write, the cache controller performs the following
sequence:
1.
2.
3.
4.
5.
With either the DXCL or DXCL2 protocol, on a single-word write, the cache controller performs the
following sequence:
1.
2.
3.
4.
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Store words from DCACHE_FSL_IN_Data to the cache
Forward the requested word to the execution unit in order to resume execution
Store remaining words from DCACHE_FSL_IN_Data to the cache
If a cache miss occurs for a load instruction or byte/halfword store instruction, which causes
the entire cache line to be read into the cache with a burst read.
All words in the cache line have been written with word store instructions.
If DCACHE_FSL_OUT_Full = 1 then stall until it goes low
Write the cache aligned address to DCACHE_FSL_OUT_Data, with the control bit set high
(DCACHE_FSL_OUT_Control = 1) to indicate a write access. The two least-significant bits
(30:31) of the address are used to encode burst access: 0b10=burst. To separate a burst access
from a single byte-write, the control bit for the first data word in step 4 is low for a burst access
(DCACHE_FSL_OUT_Control = 0).
If DCACHE_FSL_OUT_Full = 1 then stall until it goes low
Write the data to be stored to DCACHE_FSL_OUT_Data. The control bit is low
(DCACHE_FSL_OUT_Control = 0) for a burst access.
Repeat 3 and 4 for the subsequent words in the cache line.
If DCACHE_FSL_OUT_Full = 1 then stall until it goes low
Write the missed address to DCACHE_FSL_OUT_Data, with the control bit set high
(DCACHE_FSL_OUT_Control = 1) to indicate a write access. The two least-significant bits
(30:31) of the address are used to encode byte and half-word enables: 0b00=byte0, 0b01=byte1
or halfword0, 0x10=byte2, and 0x11=byte3 or halfword1. The selection of half-word or byte
access is based on the control bit for the data word in step 4.
If DCACHE_FSL_OUT_Full = 1 then stall until it goes low
Write the data to be stored to DCACHE_FSL_OUT_Data. For byte and halfword accesses the
data is mirrored onto byte-lanes. Mirroring outputs the byte or halfword to be written on all four
byte-lanes or on both halfword-lanes, respectively. The control bit should be low
(DCACHE_FSL_OUT_Control = 0) for a word or halfword access, and high for a byte access
to separate it from a burst access. Word or halfword accesses can be distinguished by the least
significant bit of the address (0=word and 1=halfword).
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Xilinx CacheLink (XCL) Interface Description
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