Xilinx MicroBlaze Reference Manual page 179

bnei
Branch Immediate if Not Equal
bnei
bneid
1 0 1 1 1 1 D 0 0 0 1
0 6
Description
Branch if rA not equal to 0, to the instruction located in the offset value of IMM. The target of the
branch will be the instruction at address PC + IMM.
The mnemonic bneid will set the D bit. The D bit determines whether there is a branch delay slot or
not. If the D bit is set, it means that there is a delay slot and the instruction following the branch (that
is, in the branch delay slot) is allowed to complete execution before executing the target instruction.
If the D bit is not set, it means that there is no delay slot, so the instruction to be executed after the
branch is the target instruction.
Pseudocode
Registers Altered
•
Latency
•
•
•
Note
By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to
use as the immediate operand. This behavior can be overridden by preceding the Type B instruction
with an imm instruction. See the instruction
values.
A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and
external hardware breaks are deferred until after the delay slot branch has been completed.
MicroBlaze Processor Reference Guide
UG081 (v14.7)
rA, IMM
rA, IMM
rA
1
1
≠
If rA 0 then
←
PC PC + sext(IMM)
else
←
PC PC + 4
if D = 1 then
allow following instruction to complete execution
PC
1 cycle (if branch is not taken, or successful branch prediction occurs)
2 cycles (if branch is taken and the D bit is set)
3 cycles (if branch is taken and the D bit is not set, or a branch prediction mispredict occurs)
www.xilinx.com
Branch Immediate if Not Equal
Branch Immediate if Not Equal with Delay
IMM
1
6
"imm," page 204 for details on using 32-bit immediate
Instructions
3
1
179
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