Xilinx MicroBlaze Reference Manual page 182

Chapter 5: MicroBlaze Instruction Set Architecture
bri
Unconditional Branch Immediate
bri
brai
brid
braid
brlid
bralid
1 0 1 1 1 0
0 6
Description
Branch to the instruction located at address determined by IMM, sign-extended to 32 bits.
The mnemonics brlid and bralid will set the L bit. If the L bit is set, linking will be performed. The
current value of PC will be stored in rD.
The mnemonics brai, braid and bralid will set the A bit. If the A bit is set, it means that the branch
is to an absolute value and the target is the value in IMM, otherwise, it is a relative branch and the
target will be PC + IMM.
The mnemonics brid, braid, brlid and bralid will set the D bit. The D bit determines whether there is
a branch delay slot or not. If the D bit is set, it means that there is a delay slot and the instruction
following the branch (that is, in the branch delay slot) is allowed to complete execution before
executing the target instruction. If the D bit is not set, it means that there is no delay slot, so the
instruction to be executed after the branch is the target instruction.
As a special case, when MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) and
"bralid rD, C_BASE_VECTORS+0x8" is used to perform a User Vector Exception, the
Machine Status Register bits User Mode and Virtual Mode are cleared.
Pseudocode
182
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IMM
IMM
IMM
IMM
rD, IMM
rD, IMM
rD D A L 0 0
1
1
if L = 1 then
←
(rD) PC
if A = 1 then
←
PC sext(IMM)
else
←
PC PC + sext(IMM)
if D = 1 then
allow following instruction to complete execution
if D = 1 and A = 1 and L = 1 and IMM = C_BASE_VECTORS+0x8 then
←
MSR[UMS] MSR[UM]
←
MSR[VMS] MSR[VM]
←
MSR[UM] 0
←
MSR[VM] 0
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Branch Immediate
Branch Absolute Immediate
Branch Immediate with Delay
Branch Absolute Immediate with Delay
Branch and Link Immediate with Delay
Branch Absolute and Link Immediate with Delay
IMM
1
6
MicroBlaze Processor Reference Guide
3
1
UG081 (v14.7)