Xilinx MicroBlaze Reference Manual page 238

Chapter 5: MicroBlaze Instruction Set Architecture
rtid
Return from Interrupt
rn from Interrupt
rtid
1 0 1 1 0 1 1 0 0 0 1
0 6
Description
Return from interrupt will branch to the location specified by the contents of rA plus the IMM field,
sign-extended to 32 bits. It will also enable interrupts after execution.
This instruction always has a delay slot. The instruction following the RTID is always executed
before the branch target. That delay slot instruction has interrupts disabled.
When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged.
This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged
Instruction exception occurs.
With low-latency interrupt mode (C_USE_INTERRUPT = 2), the Interrupt_Ack output port is set to
10 when this instruction is executed, and subsequently to 11 when the MSR{IE] bit is set.
Pseudocode
Registers Altered
•
•
•
Latency
•
Note
Convention is to use general purpose register r14 as rA.
A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and
external hardware breaks are deferred until after the delay slot branch has been completed.
238
Send Feedback
rA, IMM
rA
11
if MSR[UM] = 1 then
←
ESR[EC] 00111
else
←
(rA) + sext(IMM)
PC
←
Interrupt_Ack 10
allow following instruction to complete execution
←
MSR[IE] 1
←
MSR[UM] MSR[UMS]
←
MSR[VM] MSR[VMS]
←
Interrupt_Ack 11
PC
MSR[IE], MSR[UM], MSR[VM]
ESR[EC], in case a privileged instruction exception is generated
2 cycles
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IMM
16
MicroBlaze Processor Reference Guide
31
UG081 (v14.7)