Xilinx MicroBlaze Reference Manual page 16

Chapter 2: MicroBlaze Architecture
Table 2-6: MicroBlaze Instruction Set Summary (Continued)
Type A
Type B
RSUBKC Rd,Ra,Rb
CMP Rd,Ra,Rb
CMPU Rd,Ra,Rb
ADDI Rd,Ra,Imm
RSUBI Rd,Ra,Imm
ADDIC Rd,Ra,Imm
RSUBIC Rd,Ra,Imm
ADDIK Rd,Ra,Imm
RSUBIK Rd,Ra,Imm
ADDIKC Rd,Ra,Imm
RSUBIKC Rd,Ra,Imm
MUL Rd,Ra,Rb
MULH Rd,Ra,Rb
MULHU Rd,Ra,Rb
MULHSU Rd,Ra,Rb
BSRA Rd,Ra,Rb
BSLL Rd,Ra,Rb
MULI Rd,Ra,Imm
BSRLI Rd,Ra,Imm
BSRAI Rd,Ra,Imm
BSLLI Rd,Ra,Imm
IDIV Rd,Ra,Rb
IDIVU Rd,Ra,Rb
TNEAGETD Rd,Rb
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0-5 6-10 11-15 16-20
0-5 6-10 11-15
000111 Rd Ra
000101 Rd Ra
000101 Rd Ra
001000 Rd Ra
001001 Rd Ra
001010 Rd Ra
001011 Rd Ra
001100 Rd Ra
001101 Rd Ra
001110 Rd Ra
001111 Rd Ra
010000 Rd Ra
010000 Rd Ra
010000 Rd Ra
010000 Rd Ra
010001 Rd Ra
010001 Rd Ra
011000 Rd Ra
011001 Rd Ra
011001 Rd Ra
011001 Rd Ra
010010 Rd Ra
010010 Rd Ra
010011 Rd 00000
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21-31
16-31
Rb 00000000000 Rd := Rb + Ra + C
Rb 00000000001 Rd := Rb + Ra + 1
Rd[0] := 0 if (Rb >= Ra) else
Rd[0] := 1
Rb 00000000011 Rd := Rb + Ra + 1 (unsigned)
Rd[0] := 0 if (Rb >= Ra, unsigned) else
Rd[0] := 1
Imm Rd := s(Imm) + Ra
Imm Rd := s(Imm) + Ra + 1
Imm Rd := s(Imm) + Ra + C
Imm Rd := s(Imm) + Ra + C
Imm Rd := s(Imm) + Ra
Imm Rd := s(Imm) + Ra + 1
Imm Rd := s(Imm) + Ra + C
Imm Rd := s(Imm) + Ra + C
Rb 00000000000 Rd := Ra * Rb
Rb 00000000001 Rd := (Ra * Rb) >> 32 (signed)
Rb 00000000011 Rd := (Ra * Rb) >> 32 (unsigned)
Rb 00000000010 Rd := (Ra, signed * Rb, unsigned) >> 32
(signed)
Rb 01000000000 Rd := s(Ra >> Rb)
Rb 10000000000 Rd := (Ra << Rb) & 0
Imm Rd := Ra * s(Imm)
00000000000 & Rd : = 0 & (Ra >> Imm5)
Imm5
00000010000 & Rd := s(Ra >> Imm5)
Imm5
00000100000 & Rd := (Ra << Imm5) & 0
Imm5
Rb 00000000000 Rd := Rb/Ra
Rb 00000000010 Rd := Rb/Ra, unsigned
Rb 0N0TAE Rd := FSL Rb[28:31] (data read)
00000 MSR[FSL] := 1 if (FSL_S_Control = 1)
MSR[C] := not FSL_S_Exists if N = 1
MicroBlaze Processor Reference Guide
Semantics
UG081 (v14.7)