Xilinx MicroBlaze Reference Manual page 11

Table 2-1: Configurable Feature Overview by MicroBlaze Version
Feature
Hardware exception support
Pattern compare instructions
Floating point unit (FPU)
1
Disable hardware multiplier
Hardware debug readable ESR and EAR
Processor Version Register (PVR)
Area or speed optimized
Hardware multiplier 64-bit result
LUT cache memory
Processor Local Bus (PLB) data side interface
Processor Local Bus (PLB) instruction side
interface
Floating point conversion and square root
instructions
Memory Management Unit (MMU)
Extended stream instructions
Use Xilinx Cache Link for All I-Cache Memory
Accesses
Use Xilinx Cache Link for All D-Cache Memory
Accesses
Use Write-back Caching Policy for D-Cache
Cache Link (DXCL) protocol for D-Cache
Cache Link (IXCL) protocol for I-Cache
Branch Target Cache (BTC)
Streams for I-Cache
Victim handling for I-Cache
Victim handling for D-Cache
AXI4 (M_AXI_DP) data side interface
AXI4 (M_AXI_IP) instruction side interface
AXI4 (M_AXI_DC) protocol for D-Cache
AXI4 (M_AXI_IC) protocol for I-Cache
AXI4 protocol for stream accesses
Fault tolerant features
Tool selectable endianness
Force distributed RAM for cache tags
MicroBlaze Processor Reference Guide
UG081 (v14.7)
MicroBlaze Versions
v7.30 v8.10 v8.20
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www.xilinx.com
Overview
v8.30 v8.40 v8.50
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