Xilinx MicroBlaze Reference Manual page 31

Exception Status Register (ESR)
The Exception Status Register contains status bits for the processor. When read with the MFS
instruction, the ESR is specified by setting Sa = 0x0005. The ESR register is illustrated in
Figure
Exception Specific Status (ESS).
Table 2-11: Exception Status Register (ESR)
0:18
19
20:26
27:31
MicroBlaze Processor Reference Guide
UG081 (v14.7)
2-6, Table 2-11 provides bit descriptions and reset values, and
↑
RESERVED
Figure 2-6: ESR
Bits Name
Reserved
DS Delay Slot Exception.
0 = not caused by delay slot instruction
1 = caused by delay slot instruction
Read-only
ESS Exception Specific Status
For details refer to
Read-only
EC Exception Cause
00000 = Stream exception
00001 = Unaligned data access exception
00010 = Illegal op-code exception
00011 = Instruction bus error exception
00100 = Data bus error exception
00101 = Divide exception
00110 = Floating point unit exception
00111 = Privileged instruction exception
00111 = Stack protection violation exception
10000 = Data storage exception
10001 = Instruction storage exception
10010 = Data TLB miss exception
10011 = Instruction TLB miss exception
Read-only
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Table 2-12
19 20 26 27
↑ ¦
DS
ESS
Description
Table 2-12.
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Registers
provides the
31
↑
EC
Reset Value
0
See Table 2-12
0
31