Xilinx MicroBlaze Reference Manual page 29

Table 2-9: Machine Status Register (MSR) (Continued)
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1. The MMU exceptions (Data Storage Exception, Instruction Storage Exception, Data TLB Miss Exception,
2. This bit is only used for integer divide-by-zero or divide overflow signaling. There is a floating point equivalent
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Bits Name
C Arithmetic Carry
0 = No Carry (Borrow)
1 = Carry (No Borrow)
Read/Write
IE Interrupt Enable
0 = Interrupts disabled
1 = Interrupts enabled
Read/Write
- Reserved
Instruction TLB Miss Exception) cannot be disabled, and are not affected by this bit.
in the FSR. The DZO-bit flags divide by zero or divide overflow conditions regardless if the processor is
configured with exception handling or not.
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Registers
Reset Value
0
0
0
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